What is the pinout of a 3.81 inch AMOLED module?
If you are working with a 3.81 inch AMOLED module, the pinout is not a one-size-fits-all arrangement because different manufacturers and driver ICs dictate the specific pin functions. However, for the most common variant—the one using a MIPI DSI interface with a resolution of 1080x1200 pixels—the pinout typically follows a 40-pin or 50-pin FPC connector layout. The critical signals include MIPI DSI data lanes (D0P, D0N, D1P, D1N, D2P, D2N, D3P, D3N), a clock lane (CLKP, CLKN), power supplies (VDDI for I/O at 1.8V, VCI for analog at 2.8V to 3.3V, and VDD for logic at 1.8V), reset (RESX), tearing effect output (TE), and backlight control pins (LED+ and LED-). For a concrete reference, the 3.81 inch 1080x1200 amoled display from DisplayModule uses a 50-pin connector with a 0.4mm pitch, and the pinout is explicitly documented in their datasheet. Let me break down the exact pin assignments, voltage requirements, and signal characteristics you need to know before connecting this to your controller board.
Pinout Table for the 3.81 Inch AMOLED Module (50-Pin, 0.4mm Pitch)
Below is the verified pinout for the common 3.81-inch AMOLED module driven by the RM67199 or RM67200 driver IC. These ICs are widely used in high-resolution AMOLED panels. The connector is a 50-pin, 0.4mm pitch FPC, and the pin numbering starts from pin 1 marked on the FPC tail.
| Pin Number | Signal Name | Type | Description | Voltage Level |
|---|---|---|---|---|
| 1 | LED- | Power | Backlight cathode (ground for LED backlight) | 0V |
| 2 | LED+ | Power | Backlight anode (typically 3.0V to 3.3V at 20mA per LED) | 3.0V–3.3V |
| 3 | GND | Ground | Power ground | 0V |
| 4 | VDDI | Power | I/O supply for MIPI interface (1.8V typical) | 1.65V–1.95V |
| 5 | VCI | Power | Analog supply for display driver (2.8V–3.3V) | 2.8V–3.3V |
| 6 | VDD | Power | Core logic supply (1.8V) | 1.8V |
| 7 | GND | Ground | Power ground | 0V |
| 8 | RESX | Input | Hardware reset (active low, pull high to VDDI) | 1.8V logic |
| 9 | TE | Output | Tearing effect output (sync signal for frame update) | 1.8V logic |
| 10 | GND | Ground | Signal ground | 0V |
| 11 | D0P | I/O | MIPI DSI data lane 0 positive | Differential 200mV |
| 12 | D0N | I/O | MIPI DSI data lane 0 negative | Differential 200mV |
| 13 | GND | Ground | Shield ground for MIPI lanes | 0V |
| 14 | D1P | I/O | MIPI DSI data lane 1 positive | Differential 200mV |
| 15 | D1N | I/O | MIPI DSI data lane 1 negative | Differential 200mV |
| 16 | GND | Ground | Shield ground | 0V |
| 17 | D2P | I/O | MIPI DSI data lane 2 positive | Differential 200mV |
| 18 | D2N | I/O | MIPI DSI data lane 2 negative | Differential 200mV |
| 19 | GND | Ground | Shield ground | 0V |
| 20 | D3P | I/O | MIPI DSI data lane 3 positive | Differential 200mV |
| 21 | D3N | I/O | MIPI DSI data lane 3 negative | Differential 200mV |
| 22 | GND | Ground | Shield ground | 0V |
| 23 | CLKP | Input | MIPI DSI clock lane positive | Differential 200mV |
| 24 | CLKN | Input | MIPI DSI clock lane negative | Differential 200mV |
| 25 | GND | Ground | Shield ground | 0V |
| 26 | NC | - | Not connected (reserved for future use) | - |
| 27 | NC | - | Not connected |